The present invention relates generally to Phase locked loop frequency synthesizers and more particlarly to moduolation and compensation of such phase locked loop frequency synthesizer arrangements.
Modern-day communications systems, because of the larger number of users relying more extensively on wireless communications of all forms in conjunction with a largely fixed amount of radio spectrum, have been forced to evolve toward more spectrum efficient formats. Trunked systems, such as cellular telephone, and other centrally managed systems, with large numbers of radio frequency carriers are now the norm. In addition, utilization of digital data with greater modulation format complexity continues to increase. Thus, communications equipment for these systems must economically generate a large number of high stability radio frequency carriers and these carriers need extensive, flexible modulation capability.
Phase locked loop techiques are well known approaches to generating any one of the large number of radio frequency carriers required by todays communications systems. These techniques generally involve the application of control theory and utilize a feedback arrangement of some sort to lock a voltage controlled oscillator's frequency to a reference oscillator's frequency. The voltage controlled oscillator output then has the same inherent frequency stability as the reference oscillator at a fraction of the cost of a large number of high stability oscillators.
However, simply providing a radio frequency carrier is not enough. That carrier must convey some information. This is often accomplished by modulating the frequency of the carrier in accordance with the information or modulation signal. Therein lies a significant problem practitioners in the art must solve in one way or another. Generally the phase locked loop frequency synthesizer is designed such that its normal response to an external influence, such as modulation, is an attempt to hold the output carrier frequency invariant. Yet, to be useful, the carrier frequency must not only vary, but vary in proportion to, or largely in proportion to, a modulating signal.
Various solutions to the modulation problem have been proposed or used at one time or another. All such arrangements, however, suffer from either performance limitations (in terms of frequency response) or excessive cost, complexity or current drain. One reasonably successful approach, as disclosed in U.S. Pat. 4,775,774 to Heck, suffers because it may not proviide faithful modulation capability for non-zero average (DC) modulation or for modulation formats which include a DC component such as non-return to zero (NRZ) frequency shift keyed modulation. This places an excessive burden on the system disigner in that only modulation signals with an average value of zero can be efficiently utilized since the disclosed phase locked loop may not fully reproduce the DC component. This could prove to be a particularly significant problem at low data rate signalling or where the number of signalling levels may be significantly greater than two because the DC component of these signals may be comparatively large.
Another technique used in some prior communications systems, does provide an acceptable degree of faithful response to a non-zero average value, two-level, NRZ frequency shift keyed modulation signal. This approach consists of processing the two-level data modulation to assess its average value which is then used to adjust (i.e. by adding or subtracting pulses) the frequency of the pulse trains governing phased locked loop operation. However, this technique may well be considered excessively complex as well as costly and the operating frequencies of some of the elements may necessarily imply greater current drains. In addition, the economic burdens of extending this technique, if possible at all, to four, eight or more level frequency shift keying undeniably detract from its applicability.
Therefore, it will be appreciated that a need exists for an improved phase locked loop frequency synthesizer that is capable of being modulated by two or more level data signals where the average (DC) value of the data is non zero.